[Elphel-support] DMA transfer FPGA --> CPU

[Andrey Filippov]

Marc,

Bus master (real DMA) was implemented in hardware, but it was never
actually used. Data transfer relies on the ETRAX on-chip DMA controller,
that needs total 5 bus cycles per single 32-bit transfer. So data goes from
FPGA to ETRAX and tghen from ETRAX to memory.

Andrey

On Tue, Jan 24, 2012 at 7:25 AM, Marc Reichenbach <
marc.reichenbach at cs.fau.de> wrote:

> Hello,
>
> currently I'm trying to understand the principles of the DMA
> processing inside the camera. If I got it right the FPGA becomes a
> busmaster to write the resulting image into the systems SDRAM (later
> to be accessed by the circbuf driver).
>
> One thing is unclear to me:
> If the FPGA becomes a bus master, is the SYSCS signal (coming from the
> CPU to select the SDRAM chip - CSD0) active or not and how is it
> controlled? Since the SYS_BUSEN signal of the FPGA is always '1'
> (meaning, that the octal buffers are always disabled (high ohm-ed)), I
> have no idea how the RAM is accessed, without that CSD0 signal being high.
>
> Many thanks in advance,
>
> Marc
>
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