[Elphel-support] DMA transfer FPGA --> CPU

[Marc Reichenbach]

Hello,

currently I'm trying to understand the principles of the DMA
processing inside the camera. If I got it right the FPGA becomes a
busmaster to write the resulting image into the systems SDRAM (later
to be accessed by the circbuf driver).

One thing is unclear to me:
If the FPGA becomes a bus master, is the SYSCS signal (coming from the
CPU to select the SDRAM chip - CSD0) active or not and how is it
controlled? Since the SYS_BUSEN signal of the FPGA is always '1'
(meaning, that the octal buffers are always disabled (high ohm-ed)), I
have no idea how the RAM is accessed, without that CSD0 signal being high.

Many thanks in advance,

Marc