[Elphel-support] Project File for Xilinx softwre - Elphel353

[Andrey Filippov]

Diana,

That is a minor timing error and the camera will still work (we use rather
tight timing so it works on many cameras and conditions) , so I would not
spend much time fighting it until you need make a final bitstream. Usually
just trying different seed values with multi-pass is sufficient, and if you
did not change the code - that should be definitely possible (our posted
bitstream had 0 timing errors).

Andrey

On Thu, Aug 25, 2011 at 9:10 AM, Diana Carrigan
<DianaEJohnson at maxim-ic.com>wrote:

> It looks like there were some timing failures with Place and Route. I’ve
> attached the report.****
>
> ** **
>
> Diana****
>
> ** **
>
> *From:* elphel at gmail.com [mailto:elphel at gmail.com] *On Behalf Of *Andrey
> Filippov
> *Sent:* Tuesday, August 23, 2011 3:14 PM
> *To:* Diana Carrigan
>
> *Subject:* Re: [Elphel-support] Project File for Xilinx softwre -
> Elphel353****
>
> ** **
>
> Diana,
>
> There still may be problems when you'll run P&R - with some seed values it
> will fail completely, not just miss timing (and the "good" seed values may
> change after any modifications to the code). With proprietary, closed-source
> software tools it still remains a magic to me - make them run successfully.
>
> So if it will not work for you - please post the error messages, we'll try
> to suggest solutions.
>
> For simulation (provided you installed Icarus Verilog and GTK Wave as
> written on our Wiki) you may run
> ./x353_sim.sh
> script from the  fpga/x353 subdirectory.
>
> Andrey****
>
> On Tue, Aug 23, 2011 at 1:44 PM, Diana Carrigan <
> DianaEJohnson at maxim-ic.com> wrote:****
>
> Excellent! You guys rock!****
>
>  ****
>
> Diana****
>
>  ****
>
> *From:* elphel at gmail.com [mailto:elphel at gmail.com] *On Behalf Of *Andrey
> Filippov
> *Sent:* Tuesday, August 23, 2011 12:38 PM
> *To:* Diana Carrigan; support-list at support.elphel.com
> *Subject:* Re: [Elphel-support] Project File for Xilinx softwre -
> Elphel353****
>
>  ****
>
> Diana,
>
> Yes, sure - you can go to Project->Source Control->Import
> and select x353_import.tcl
> That will create Xilinx ISE  *.ise project file.
>
> Andrey
>
> ****
>
> On Tue, Aug 23, 2011 at 10:04 AM, Diana Carrigan <
> DianaEJohnson at maxim-ic.com> wrote:****
>
> Hello****
>
>  ****
>
> I was just wondering if you guys had  a  “project” file already setup for
> the FPGA in the Elphl353. I noticed the x353.ucf file has the
> Project:~/PCB/10353/REVB/10353B mentioned. Can this be downloaded from your
> website, or should I create a new project and just add all of the source
> files from the “fpga” directory?? ****
>
>  ****
>
> Diana****
>
>
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> ****
>
>  ****
>
>
> _______________________________________________
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>
> ** **
>
> _______________________________________________
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