[Elphel-support] mcontr353 question

[Marc Reichenbach]

Dear Elphel Team,

I've got a small question about the memory controller in x353. The
memory controllers has 4 channels, where channel 0 is for the
sensor-output. The memorycontroller is controlled by the writepage
signal, which stores all temporary data (stored in BRAM) to the DDR
RAM. The adress to the memory controller is only 10 bit (2MSB for
bank, 8 for local adressing). My question is, how are the global
adresses (for the ddr ram) are calculated? For example in the
simulation the data for bank 0 can be stored at 0+x, 160+x, 320+x and
so on, where x is the local (BRAM) address. But how is the "offset"
(0,160,320, ..) calculated. My first idea was, it is increased by
every cycle where writepage is 1. But now I think, it is time
depending. Could you please tell me, where this adress is calculated
(which module/verilog file/line) and how it works?

Thank you for your efforts,

Marc

PS: Sebastian Pichelhofer has asked me, if I can a little bit
documented my research work (for example: the simulation with VCS).
Should I do this in the wiki below UserProjects?