[Elphel-support] Status of Theora FPGA encoder

[Sebastien Bourdeauducq]

Hi,

thanks for your answers.

On Thu, 2011-05-05 at 12:46 -0600, Andrey Filippov wrote:
> There are several "natural" domains - sync to sensor pixel clock,
> memory and compressor. Each of them I wanted to have separate clock so
> I could tune to the maximum performance.

Ok, understood, I don't question these ones.

> Additionally I tried to use multiple phases of the clock to spread
> register transitions in time - in the older 313 camera I had some
> problems with data integrity because of the spikes on the ground/power
> lines caused by massive simultaneous register transitions.

Are you sure this has to do with power integrity? During the design of
Milkymist SoC, I sometimes experienced bugs in the Xilinx timing models
that manifested themselves with the design meeting timing according to
the tools when in fact it did not. Freezing the FPGA to several degrees
below zero made the design work, until the timing bugs were finally
fixed.

Another rare and annoying problem with FPGAs is internal crosstalk,
which is poorly handled by the tools. Apparently, the ASIC industry
threw a lot of research into modeling and preventing crosstalk in the
EDA tools, while the FPGA people felt there was not such a big need for
this. It is mentioned e.g. in
http://portal.acm.org/citation.cfm?id=1667523
I can mail you the PDF if you don't have an account with those ACM
a**holes.

> I still try to balance register transitions during clock period.

That's an interesting design technique. Have you heard of other designs
or publications doing the same? Do you have some more documentation or
information about this, e.g. precise measurements of how noise is
reduced by doing so?

FWIW, Google boasts that its hardware VP8 encoder and decoder are fully
synchronous.

Thanks,
Sébastien