[Elphel-support] Questions about 10359 and wavelet transformatoin

[Oleg K Dzhimiev]

Dear Jens,

So with the lower 7 bits of the i2c-address I can control what data is
> assigned to
> the i2c_do, right?
> i2c_do has 32 bits and the possibilities are the wires assigned in the
> preceeding
> lines, like for example
> wire [31:0] r_02 = {16'b0,ddr_do[15:0]};
>
I didn't really find where one can choose the address to be read from, and
> what do
> you mean by "8-bit-addresses"? I see that there are only 8 bits left in the
> i2c-reg.
>

The I2C serial sequence is *<8bit SLAVE R/W ADDR><8bit REG ADDRESS>*<16bit
DATA when W>. It all goes through "i2c_sr" (and "i2c_reg_addr" as well):

> i2c_sr[7:0] -> i2c_reg_addr[7:0]
>
And once the i2c slave address is latched (x359.v line 922) - the register
address is the following 8 bits. For read for example:

> i2c_sr[7:0] -> i2c_reg_addr[7:0] -> ia[6:0]
>
"ia" will define what register go to i2c_do (the mux described in x359.v,
line 3542)

How I can access the memory? Are there hints what the memory layout is like
> resp. how mcontr does abstract from the SDRAM?
>

SDRAM transactions (by mcontr) are the following:

Init:
After the power on it should be initialized (described in the datasheet and
in x359.tf).

Write:
a. fill an mcontr's buffer of the corresponding channel (chX_ibwe - we,
chX_a - buffer address, chX_ibdat - data)
b. issue a command for page write (chX_next_line & chX_last_line - page
write, 1 clock period long)

Read:
a. issue a command for page read (chX_start - page read, 1 clock period
long)
b. readout a page from from an mcontr's buffer of the read channel (chXa -
buffer address, chXdo - data).

Rewrite mcontr's channels parameters like the SDRAM page address (auto
incremented) or page address boundaries:
a. 0x850 - "da_dswe_high" - for the 16-bit MSB part
b. 0x84X - "da_dswe" - 16-bit LSB part and the word write to the X register
to the mcontr:
mcontr_cmd.v (line 189):

>     mwr_cmd    <= mwr && (ma[4:0]==5'h0);
>     mancmd_stb <= mwr && (ma[4:0]==5'h1);
>     mwr_nxny   <= mwr && (ma[4:0]==5'h2);
>     mwr_tkpars <= mwr && (ma[4:0]==5'h3);
>     mwr_ch0    <= mwr && (ma[4:0]==5'h4);
>     mwr_ch1    <= mwr && (ma[4:0]==5'h5);
>     mwr_ch2    <= mwr && (ma[4:0]==5'h6);
>     mwr_ch3    <= mwr && (ma[4:0]==5'h7);
>     mwr_ch0x  <= mwr & (ma[4:0]==5'h0c);
>     mwr_ch1x  <= mwr & (ma[4:0]==5'h0d);
>     mwr_ch0y  <= mwr & (ma[4:0]==5'h0e);
>     mwr_ch1y  <= mwr & (ma[4:0]==5'h0f);
>

Additional info (you probably already read it but anyway):

1. Schematics:
A link from 10359's wiki page http://wiki.elphel.com/index.php?title=10359:
10359 Circuit Diagram, Parts List, PCB
layout<http://wiki.elphel.com/images/0/01/10359.pdf>

2. MT46V32M16BN-5B datasheet:
http://download.micron.com/pdf/datasheets/dram/ddr/512MBDDRx4x8x16.pdf

So data is read from the SDRAM via channel 5 and in 2-byte-blocks?
>
Yes. Channels 4 & 5 were made for testing - this is why ddr_do goes to i2c
register.


> "no buffering" - the direct channels are enabled/disabled in turns - not
> > synchronized.
> What does "not synchronized" mean?
>
I wasn't clear, sorry. The case is for 2 sensors connected. And by channels
here I meant 'sensors'. "The direct channels are enabled/disabled in turns"
- let's say the sensors are synchronized (triggered at the same time) - then
"with buffering" you get a couple of images for the same moment of time, W/o
buffering - single image.

Do you have simulation working? Let's fix it, so you could monitor the
waves.

Best regards,
Oleg
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