[Elphel-support] download a bitstream to Spartan 3e FPGA in 10353

[Jens Bürger]

Am 10.11.2010 um 15:01 schrieb Sol Pedre:

> Hello,

Hello Sol,
> 
> 1) I'm starting to develop using a 353 camera. I need to change the
> FPGA code but I don't find the JTAG port exported.

Sounds interesting, what are you going to do?

> I wanted to know
> how to download a bitstream to the Spartan FPGA in the board.

Every time the camera boots, the FPGA is configured using the /etc/init.d/fpga
script.
It estimates the suitable .bit-images and writes it to the FPGA.
The images are located here:
/mnt/flash/etc/x347.bit
/mnt/flash/etc/x353.bit
/mnt/flash/etc/x359.bit

So everything you have to do is put a new .bit-images onto the flash-ram of the camera (using scp for instance) and do a reboot.

> 2) I also read in this mailing list that there was some trouble using
> ISE Design Suite 11, that is the xilinx design suite I use. Is that
> problem fixed?

Not really, AFAIK.
As far as i know, the FPGA-code is designed using OSS mainly (Icarus Verilog, Kdevelop,...). Xilinx ISE (the WebPACK will do) is primarily used for the pure synthesis-process and for getting the Verilog-sources of some Xilinx primitive cores (like shift register and block-RAM).

I'm currently working in a student university project trying to implement additional features on the FPGA (consider my e-mail from today). As we aren't that into FPGA-development, we appreciate the tool support of an IDE very much and thus are using Xilinx ISE (currently 11, we've done some tests with 12).

To make at least ISE 11 build the project, you have got to alter the last lines of quantizator353.v as follows:
//synthesis attribute INIT of i_z0  is 32'hC67319CC; 
//synthesis attribute INIT of i_z1  is 32'h611A7896; 
//synthesis attribute INIT of i_z2  is 32'h6357A260;
//synthesis attribute INIT of i_z3  is 32'h4A040C18; 
//synthesis attribute INIT of i_z4  is 32'h8C983060; 
//synthesis attribute INIT of i_z5  is 32'hF0E0C080;

To make ISim work, we did the additional two changes:

In x353.v line 1464, comment:
defparam i_dcr_31.INIT = 1'b1;

In ddr.v line 228, comment:
wire Debug = 1'b1;

HTH,
Jens