[Elphel-support] Fpga build using ISE 11.1

[Andrey Filippov]

André,

I tried again to convert the project to to the current WebPack 11.5 and so
far it did not work. I opened the existent *.ise project and made *.xise
file. Then deleted all but Verilog source files and x353.ucf constraints
file.

At the first run Translate failed - it did not like ROM32x1 initialization
with "//synthesis attribute INIT..." at the end of quantizator353.v so I
fixed it, but the I could not get through Map (reported 4 errors). I tried
temporarily removing all the constraints from the x353.ucf but the pinout,
and still I got the same 4 Mapper errors:

ERROR:Place:1120 - Big block initial random placer cannot find solution.
This is  due to design being overconstrained by user specified or clock
region
   constraints. Try locking down the big blocks to improve this condition.
ERROR:Place:543 - This design does not fit into the number of slices
available    in this device due to the complexity of the design and/or
constraints.
ERROR:Place:120 - There were not enough sites to place all selected
components.
ERROR:Pack:1654 - The timing-driven placement phase encountered an error.

Same design in 10.1.03 works OK, utilization is not too high:

Design Summary Report:
 Number of External IOBs                         142 out of 190    74%
   Number of External Input IOBs                 35
      Number of External Input DIFFMIs            1
        Number of LOCed External Input DIFFMIs    1 out of 1     100%
      Number of External Input DIFFSIs            1
        Number of LOCed External Input DIFFSIs    1 out of 1     100%
      Number of External Input IBUFs             33
        Number of LOCed External Input IBUFs     33 out of 33    100%
   Number of External Output IOBs                37
      Number of External Output DIFFMs            1
        Number of LOCed External Output DIFFMs    1 out of 1     100%
      Number of External Output DIFFSs            1
        Number of LOCed External Output DIFFSs    1 out of 1     100%
      Number of External Output IOBs             35
        Number of LOCed External Output IOBs     35 out of 35    100%
   Number of External Bidir IOBs                 70
      Number of External Bidir IOBs              70
        Number of LOCed External Bidir IOBs      70 out of 70    100%
   Number of BUFGMUXs                        9 out of 24     37%
   Number of DCMs                            4 out of 8      50%
   Number of MULT18X18SIOs                  19 out of 28     67%
   Number of RAMB16s                        21 out of 28     75%
   Number of Slices                       5925 out of 8672   68%
      Number of SLICEMs                    354 out of 4336    8%


Andrey
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